-------------------------------------------------------------------------------
-- CSE 471 HW #2 ; VHDL Design
-- Section : 2
-- Designer : Meghan Hoke
-- Date : 8/30/2001
-- File : add4rca.vhd
-- Description : 4 bit ripple carry adder
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity add4rca is
    
    port (a, b : in std_logic_vector(3 downto 0);
	  ci : in std_logic;
	  s : out std_logic_vector(3 downto 0) ;
	  co : out std_logic);

end add4rca;

architecture struc of add4rca is

    component fa1
	port (a, b, ci : in std_logic;
	      s, co : out std_logic);
    end component;

    for all: fa1 use entity work.fa1(struc);

    signal c : std_logic_vector(3 downto 1);
    
begin  -- struc
    fx0: fa1 port map (a(0), b(0), ci, s(0), c(1));
    fx1: fa1 port map (a(1), b(1), c(1), s(1), c(2));
    fx2: fa1 port map (a(2), b(2), c(2), s(2), c(3));
    fx3: fa1 port map (a(3), b(3), c(3), s(3), co);
end struc;