--------------------------------------------------------------------------------
-- CSE 471 HW #2 ; VHDL Design
-- Section : 2
-- Designer : Meghan Hoke
-- Date : 8/30/2001
-- File : fa1.vhd
-- Description : 1 bit full adder
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity fa1 is
    
    port (a, b, ci : in std_logic;
	  s, co : out std_logic);

end fa1;

architecture struc of fa1 is

    component not1
	port (a : in std_logic;
	      z : out std_logic);
    end component;

    component nand2
	port (a, b : in std_logic;
	      z : out std_logic);
    end component;

    component nand3
	port (a, b, c : in std_logic;
	      z : out std_logic);
    end component;

    component nand4
	port (a, b, c, d : in std_logic;
	      z : out std_logic);
    end component;

    for all: not1 use entity work.not1(beha);
    for all: nand2 use entity work.nand2(beha);
    for all: nand3 use entity work.nand3(beha);
    for all: nand4 use entity work.nand4(beha);

    signal a_n, b_n, ci_n : std_logic;
    signal x0, x1, x2, y0, y1, y2, y3 : std_logic;
    
begin  -- struc
    iw0: not1 port map (a, a_n);
    iw1: not1 port map (b, b_n);
    iw2: not1 port map (ci, ci_n);
    ix0: nand2 port map (a, b, x0);
    ix1: nand2 port map (a, ci, x1);
    ix2: nand2 port map (b, ci, x2);
    fx0: nand3 port map (x0, x1, x2, co);
    iy0: nand3 port map (a, b, ci, y0);
    iy1: nand3 port map (a_n, b_n, ci, y1);
    iy2: nand3 port map (a_n, b, ci_n, y2);
    iy3: nand3 port map (a, b_n, ci_n, y3);
    fy0: nand4 port map (y0, y1, y2, y3, s);
end struc;