-------------------------------------------------------------------------------
-- CSE 471 Project #2 ; Program Counter Design
-- Section : 2
-- Designer : Meghan Hoke
-- Date : 9/18/2001
-- File : mux.vhd
-- Description : 2 to 1 multiplexer
-- delay = 32 ns
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity mux is
    
    port (d0, d1 : in std_logic_vector(3 downto 0);
	  s : in std_logic;
	  z : out std_logic_vector(3 downto 0));

end mux;

architecture struc of mux is

    signal sinv, s1, s2, s3, s4, s5, s6, s7, s8 : std_logic;

begin
    sinv <= not s after 10 ns;

    s1 <= d1(0) nand s after 11 ns;
    s2 <= d0(0) nand sinv after 11 ns;
    z(0) <= s1 nand s2 after 11 ns;

    s3 <= d1(1) nand s after 11 ns;
    s4 <= d0(1) nand sinv after 11 ns;
    z(1) <= s3 nand s4 after 11 ns;

    s5 <= d1(2) nand s after 11 ns;
    s6 <= d0(2) nand sinv after 11 ns;
    z(2) <= s5 nand s6 after 11 ns;

    s7 <= d1(3) nand s after 11 ns;
    s8 <= d0(3) nand sinv after 11 ns;
    z(3) <= s7 nand s8 after 11 ns;
end struc;