-------------------------------------------------------------------------------
-- CSE 471 Project #3 ; 4-bit Multiplier Design
-- Section : 2
-- Designer : Meghan Hoke
-- Date : 10/4/2001
-- File : add8rca.vhd
-- Description : 8 bit ripple carry adder
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity add8rca is
    
    port (a, b : in std_logic_vector(7 downto 0);
	  ci : in std_logic;
	  s : out std_logic_vector(7 downto 0) ;
	  co : out std_logic);

end add8rca;

architecture struc of add8rca is

    component fa1
	port (a, b, ci : in std_logic;
	      s, co : out std_logic);
    end component;

    for all: fa1 use entity work.fa1(struc);

    signal c : std_logic_vector(7 downto 1);
    
begin  -- struc
    fx0: fa1 port map (a(0), b(0), ci, s(0), c(1));
    fx1: fa1 port map (a(1), b(1), c(1), s(1), c(2));
    fx2: fa1 port map (a(2), b(2), c(2), s(2), c(3));
    fx3: fa1 port map (a(3), b(3), c(3), s(3), c(4));
    fx4: fa1 port map (a(4), b(4), c(4), s(4), c(5));
    fx5: fa1 port map (a(5), b(5), c(5), s(5), c(6));
    fx6: fa1 port map (a(6), b(6), c(6), s(6), c(7));
    fx7: fa1 port map (a(7), b(7), c(7), s(7), co);
end struc;