-------------------------------------------------------------------------------
-- CSE 471 Project #3 ; 4-bit Multiplier Design
-- Section : 2
-- Designer : Meghan Hoke
-- Date : 10/4/2001
-- File : counter.vhd
-- Description : 8 bit Program Counter
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity counter is
    
    port (b : in std_logic_vector(7 downto 0);
	  r, w : in std_logic;
          a : out std_logic_vector(7 downto 0));

end counter;

architecture struc of counter is

    component mux
	port (d0, d1 : in std_logic_vector(7 downto 0);
	      s : in std_logic;
	      z : out std_logic_vector(7 downto 0));
    end component;

    component flipflop
	port (d : in std_logic_vector(7 downto 0);
	      w : in std_logic;
	      q : out std_logic_vector(7 downto 0));
    end component;

    component add8rca
	port (a, b : in std_logic_vector(7 downto 0);
	      ci : in std_logic;
	      s : out std_logic_vector(7 downto 0);
	      co : out std_logic);
    end component;

    for all: mux use entity work.mux(struc);
    for all: flipflop use entity work.flipflop(struc);
    for all: add8rca use entity work.add8rca(struc);

    signal cin, cout : std_logic := '0';
    signal sum, mux0,s : std_logic_vector(7 downto 0);
    signal mux1 : std_logic_vector(7 downto 0) := "00000000";

begin  -- struc
    a1: add8rca port map (s, b, cin, sum, cout);
    m1: mux port map (sum, mux1, r, mux0);
    l1: flipflop port map (mux0, w, s);
    a <= s;
end struc;