-------------------------------------------------------------------------------
-- CSE 471 Project #3 ; 4 bit Multiplier Design
-- Section : 2
-- Designer : Meghan Hoke
-- Date : 10/4/2001
-- File : dlatch.vhd
-- Description : 8 bit D-Latch
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity dlatch is
    
    port (d : in std_logic_vector(7 downto 0);
	  write : in std_logic;
	  q : out std_logic_vector(7 downto 0));

end dlatch;

architecture struc of dlatch is

    component mux
	port (d0, d1 : in std_logic_vector(7 downto 0);
	      s : in std_logic;
	      z : out std_logic_vector(7 downto 0));
    end component;

    for all: mux use entity work.mux(struc);

    signal s : std_logic_vector(7 downto 0);

begin  -- struc
    m1: mux port map (s, d, write, s);
    q <= s;
end struc;