-------------------------------------------------------------------------------
-- CSE 471 HW #2 ; VHDL Design
-- Section : 2
-- Designer : Meghan Hoke
-- Date : 8/30/2001
-- File : nand4.vhd
-- Description : 4 input nand gate
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity nand4 is
    
    port (a, b, c, d : in std_logic;
	  z : out std_logic);

end nand4;

architecture beha of nand4 is
    
begin  -- beha
    z <= (not (a and b and c and d)) after 13 ns;
end beha;