-------------------------------------------------------------------------------
-- CSE 471 HW #2 ; VHDL Design
-- Section : 2
-- Designer : Meghan Hoke
-- Date : 8/30/2001
-- File : not1.vhd
-- Description : inverter
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity not1 is    

    port (a : in std_logic;
	  z : out std_logic);

end not1;

architecture beha of not1 is
    
begin  -- beha
    z <= (not a) after 10 ns;
end beha;