-------------------------------------------------------------------------------
-- CSE 471 Project #3 ; 4-bit Multiplier Design
-- Section : 2
-- Designer : Meghan Hoke
-- Date : 10/4/2001
-- File : ufmd.vhd
-- Description : 4 bit Ultra Fast Multiplier
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use STD.STANDARD.all;

entity ufmd is
    
    port (input : in std_logic_vector(7 downto 0);  -- input bits
	  r, ck : in std_logic;  	      -- reset, clock bit
	  c : out std_logic_vector(7 downto 0));   -- output bits

end ufmd;

architecture struc of ufmd is

    component counter
	port (b : in std_logic_vector(7 downto 0);
	      r,w : in std_logic;
	      a : out std_logic_vector(7 downto 0));
    end component;

    component rom
	port (r0, r1, r2, r3, r4, r5, r6, r7 : in std_logic;
	      m0, m1, m2, m3, m4, m5, m6, m7 : out std_logic);
    end component;

    for all: counter use entity work.counter(struc);
    for all: rom use entity work.rom(struc);

    signal a : std_logic_vector(7 downto 0);
    signal i: integer;
    
begin
    c1: counter port map (input, r, ck, a);
    r1: rom port map (a(0), a(1), a(2), a(3), a(4), a(5), a(6), a(7),
	              c(0), c(1), c(2), c(3), c(4), c(5), c(6), c(7));
end struc;