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-- CSE 471 Project #4 ; 2kbit Static RAM Design
-- Section : 2
-- Designer : Meghan Hoke
-- Date : 10/25/01
-- File : sram.vhd
-- Description : 2kbit SRAM
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library IEEE;
use IEEE.std_logic_1164.all;

entity sram is
    port (address : in std_logic_vector(7 downto 0);  -- address bits
	  csb : in std_logic;  		-- chip select bit
	  web : in std_logic;  		-- write enable bit
	  oeb : in std_logic;  		-- output enable bit
	  data : inout std_logic_vector(7 downto 0)); -- datapath bits
end sram;

architecture struc of sram is

    component tris8
	port(a : in std_logic_vector(7 downto 0);
	     s : in std_logic;  
	     z : inout std_logic_vector(7 downto 0));
    end component;

    component memarray
	port(decoder : in std_logic_vector(255 downto 0);
	     datain  : in std_logic_vector(7 downto 0);
	     write   : in std_logic;  
	     dataout : inout std_logic_vector(7 downto 0));
    end component;

    component decoder
	port(address : in std_logic_vector(7 downto 0);
	     decoderout : out std_logic_vector(255 downto 0));
    end component;

    component control
	port(csb, web, oeb : in std_logic;
	     write, read : out std_logic);
    end component;

    for all: tris8 use entity work.tris8(beha);
    for all: memarray use entity work.memarray(struc);
    for all: decoder use entity work.decoder(struc);
    for all: control use entity work.control(struc);

    signal decout : std_logic_vector(255 downto 0);
    signal latchout, triout, output : std_logic_vector(7 downto 0);
    signal write, read : std_logic;

begin
    d0: decoder port map (address, decout);
    c0: control port map (csb, web, oeb, write, read);
    m0: memarray port map (decout, data, write, output);
    t0: tris8  port map (output, read, triout);
    data <= triout;
end struc;