-----------------------------------------------------------
-- CSE 471 Project #5 ; 8-bit Microcontroller Design
-- Section : 2
-- Designer : Meghan Hoke
-- Date : 11/15/01
-- File : array.vhd
-- Description : 256 x 8 Memory Array
-----------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity memarray is
   port(decoder : in std_logic_vector(255 downto 0);
        datain  : in std_logic_vector(7 downto 0);
	write   : in std_logic;  
        dataout : inout std_logic_vector(7 downto 0));
end memarray;

architecture struc of memarray is

    component tris8
	port(a : in std_logic_vector(7 downto 0);
	     s : in std_logic;  
	     z : inout std_logic_vector(7 downto 0));
    end component;

    component dlatch
        port (d : in std_logic_vector(7 downto 0);
	      write : in std_logic;
	      q : out std_logic_vector(7 downto 0));
    end component;

    for all: tris8 use entity work.tris8(beha);
    for all: dlatch use entity work.dlatch(struc);

    signal and2 : std_logic_vector(255 downto 0);
    signal latchout : std_logic_vector(7 downto 0);
    
begin
    and2(0) <= write and decoder(0) after 14 ns;
    d0: dlatch port map (datain, and2(0), latchout);
    t0: tris8  port map (latchout, decoder(0), dataout);

    and2(1) <= write and decoder(1) after 14 ns;
    d1: dlatch port map (datain, and2(1), latchout);
    t1: tris8  port map (latchout, decoder(1), dataout);

    and2(2) <= write and decoder(2) after 14 ns;
    d2: dlatch port map (datain, and2(2), latchout);
    t2: tris8  port map (latchout, decoder(2), dataout);

    and2(3) <= write and decoder(3) after 14 ns;
    d3: dlatch port map (datain, and2(3), latchout);
    t3: tris8  port map (latchout, decoder(3), dataout);

    and2(4) <= write and decoder(4) after 14 ns;
    d4: dlatch port map (datain, and2(4), latchout);
    t4: tris8  port map (latchout, decoder(4), dataout);

    and2(5) <= write and decoder(5) after 14 ns;
    d5: dlatch port map (datain, and2(5), latchout);
    t5: tris8  port map (latchout, decoder(5), dataout);

    and2(6) <= write and decoder(6) after 14 ns;
    d6: dlatch port map (datain, and2(6), latchout);
    t6: tris8  port map (latchout, decoder(6), dataout);

    and2(7) <= write and decoder(7) after 14 ns;
    d7: dlatch port map (datain, and2(7), latchout);
    t7: tris8  port map (latchout, decoder(7), dataout);

    and2(8) <= write and decoder(8) after 14 ns;
    d8: dlatch port map (datain, and2(8), latchout);
    t8: tris8  port map (latchout, decoder(8), dataout);

    and2(9) <= write and decoder(9) after 14 ns;
    d9: dlatch port map (datain, and2(9), latchout);
    t9: tris8  port map (latchout, decoder(9), dataout);

    and2(10) <= write and decoder(10) after 14 ns;
    d10: dlatch port map (datain, and2(10), latchout);
    t10: tris8  port map (latchout, decoder(10), dataout);

    and2(11) <= write and decoder(11) after 14 ns;
    d11: dlatch port map (datain, and2(11), latchout);
    t11: tris8  port map (latchout, decoder(11), dataout);

    and2(12) <= write and decoder(12) after 14 ns;
    d12: dlatch port map (datain, and2(12), latchout);
    t12: tris8  port map (latchout, decoder(12), dataout);

    and2(13) <= write and decoder(13) after 14 ns;
    d13: dlatch port map (datain, and2(13), latchout);
    t13: tris8  port map (latchout, decoder(13), dataout);

    and2(14) <= write and decoder(14) after 14 ns;
    d14: dlatch port map (datain, and2(14), latchout);
    t14: tris8  port map (latchout, decoder(14), dataout);

    and2(15) <= write and decoder(15) after 14 ns;
    d15: dlatch port map (datain, and2(15), latchout);
    t15: tris8  port map (latchout, decoder(15), dataout);

    and2(16) <= write and decoder(16) after 14 ns;
    d16: dlatch port map (datain, and2(16), latchout);
    t16: tris8  port map (latchout, decoder(16), dataout);

    and2(17) <= write and decoder(17) after 14 ns;
    d17: dlatch port map (datain, and2(17), latchout);
    t17: tris8  port map (latchout, decoder(17), dataout);

    and2(18) <= write and decoder(18) after 14 ns;
    d18: dlatch port map (datain, and2(18), latchout);
    t18: tris8  port map (latchout, decoder(18), dataout);

    and2(19) <= write and decoder(19) after 14 ns;
    d19: dlatch port map (datain, and2(19), latchout);
    t19: tris8  port map (latchout, decoder(19), dataout);

    and2(20) <= write and decoder(20) after 14 ns;
    d20: dlatch port map (datain, and2(20), latchout);
    t20: tris8  port map (latchout, decoder(20), dataout);

    and2(21) <= write and decoder(21) after 14 ns;
    d21: dlatch port map (datain, and2(21), latchout);
    t21: tris8  port map (latchout, decoder(21), dataout);

    and2(22) <= write and decoder(22) after 14 ns;
    d22: dlatch port map (datain, and2(22), latchout);
    t22: tris8  port map (latchout, decoder(22), dataout);

    and2(23) <= write and decoder(23) after 14 ns;
    d23: dlatch port map (datain, and2(23), latchout);
    t23: tris8  port map (latchout, decoder(23), dataout);

    and2(24) <= write and decoder(24) after 14 ns;
    d24: dlatch port map (datain, and2(24), latchout);
    t24: tris8  port map (latchout, decoder(24), dataout);

    and2(25) <= write and decoder(25) after 14 ns;
    d25: dlatch port map (datain, and2(25), latchout);
    t25: tris8  port map (latchout, decoder(25), dataout);

    and2(26) <= write and decoder(26) after 14 ns;
    d26: dlatch port map (datain, and2(26), latchout);
    t26: tris8  port map (latchout, decoder(26), dataout);

    and2(27) <= write and decoder(27) after 14 ns;
    d27: dlatch port map (datain, and2(27), latchout);
    t27: tris8  port map (latchout, decoder(27), dataout);

    and2(28) <= write and decoder(28) after 14 ns;
    d28: dlatch port map (datain, and2(28), latchout);
    t28: tris8  port map (latchout, decoder(28), dataout);

    and2(29) <= write and decoder(29) after 14 ns;
    d29: dlatch port map (datain, and2(29), latchout);
    t29: tris8  port map (latchout, decoder(29), dataout);

    and2(30) <= write and decoder(30) after 14 ns;
    d30: dlatch port map (datain, and2(30), latchout);
    t30: tris8  port map (latchout, decoder(30), dataout);

    and2(31) <= write and decoder(31) after 14 ns;
    d31: dlatch port map (datain, and2(31), latchout);
    t31: tris8  port map (latchout, decoder(31), dataout);

    and2(32) <= write and decoder(32) after 14 ns;
    d32: dlatch port map (datain, and2(32), latchout);
    t32: tris8  port map (latchout, decoder(32), dataout);

    and2(33) <= write and decoder(33) after 14 ns;
    d33: dlatch port map (datain, and2(33), latchout);
    t33: tris8  port map (latchout, decoder(33), dataout);

    and2(34) <= write and decoder(34) after 14 ns;
    d34: dlatch port map (datain, and2(34), latchout);
    t34: tris8  port map (latchout, decoder(34), dataout);

    and2(35) <= write and decoder(35) after 14 ns;
    d35: dlatch port map (datain, and2(35), latchout);
    t35: tris8  port map (latchout, decoder(35), dataout);

    and2(36) <= write and decoder(36) after 14 ns;
    d36: dlatch port map (datain, and2(36), latchout);
    t36: tris8  port map (latchout, decoder(36), dataout);

    and2(37) <= write and decoder(37) after 14 ns;
    d37: dlatch port map (datain, and2(37), latchout);
    t37: tris8  port map (latchout, decoder(37), dataout);

    and2(38) <= write and decoder(38) after 14 ns;
    d38: dlatch port map (datain, and2(38), latchout);
    t38: tris8  port map (latchout, decoder(38), dataout);

    and2(39) <= write and decoder(39) after 14 ns;
    d39: dlatch port map (datain, and2(39), latchout);
    t39: tris8  port map (latchout, decoder(39), dataout);

    and2(40) <= write and decoder(40) after 14 ns;
    d40: dlatch port map (datain, and2(40), latchout);
    t40: tris8  port map (latchout, decoder(40), dataout);

    and2(41) <= write and decoder(41) after 14 ns;
    d41: dlatch port map (datain, and2(41), latchout);
    t41: tris8  port map (latchout, decoder(41), dataout);

    and2(42) <= write and decoder(42) after 14 ns;
    d42: dlatch port map (datain, and2(42), latchout);
    t42: tris8  port map (latchout, decoder(42), dataout);

    and2(43) <= write and decoder(43) after 14 ns;
    d43: dlatch port map (datain, and2(43), latchout);
    t43: tris8  port map (latchout, decoder(43), dataout);

    and2(44) <= write and decoder(44) after 14 ns;
    d44: dlatch port map (datain, and2(44), latchout);
    t44: tris8  port map (latchout, decoder(44), dataout);

    and2(45) <= write and decoder(45) after 14 ns;
    d45: dlatch port map (datain, and2(45), latchout);
    t45: tris8  port map (latchout, decoder(45), dataout);

    and2(46) <= write and decoder(46) after 14 ns;
    d46: dlatch port map (datain, and2(46), latchout);
    t46: tris8  port map (latchout, decoder(46), dataout);

    and2(47) <= write and decoder(47) after 14 ns;
    d47: dlatch port map (datain, and2(47), latchout);
    t47: tris8  port map (latchout, decoder(47), dataout);

    and2(48) <= write and decoder(48) after 14 ns;
    d48: dlatch port map (datain, and2(48), latchout);
    t48: tris8  port map (latchout, decoder(48), dataout);

    and2(49) <= write and decoder(49) after 14 ns;
    d49: dlatch port map (datain, and2(49), latchout);
    t49: tris8  port map (latchout, decoder(49), dataout);

    and2(50) <= write and decoder(50) after 14 ns;
    d50: dlatch port map (datain, and2(50), latchout);
    t50: tris8  port map (latchout, decoder(50), dataout);

    and2(51) <= write and decoder(51) after 14 ns;
    d51: dlatch port map (datain, and2(51), latchout);
    t51: tris8  port map (latchout, decoder(51), dataout);

    and2(52) <= write and decoder(52) after 14 ns;
    d52: dlatch port map (datain, and2(52), latchout);
    t52: tris8  port map (latchout, decoder(52), dataout);

    and2(53) <= write and decoder(53) after 14 ns;
    d53: dlatch port map (datain, and2(53), latchout);
    t53: tris8  port map (latchout, decoder(53), dataout);

    and2(54) <= write and decoder(54) after 14 ns;
    d54: dlatch port map (datain, and2(54), latchout);
    t54: tris8  port map (latchout, decoder(54), dataout);

    and2(55) <= write and decoder(55) after 14 ns;
    d55: dlatch port map (datain, and2(55), latchout);
    t55: tris8  port map (latchout, decoder(55), dataout);

    and2(56) <= write and decoder(56) after 14 ns;
    d56: dlatch port map (datain, and2(56), latchout);
    t56: tris8  port map (latchout, decoder(56), dataout);

    and2(57) <= write and decoder(57) after 14 ns;
    d57: dlatch port map (datain, and2(57), latchout);
    t57: tris8  port map (latchout, decoder(57), dataout);

    and2(58) <= write and decoder(58) after 14 ns;
    d58: dlatch port map (datain, and2(58), latchout);
    t58: tris8  port map (latchout, decoder(58), dataout);

    and2(59) <= write and decoder(59) after 14 ns;
    d59: dlatch port map (datain, and2(59), latchout);
    t59: tris8  port map (latchout, decoder(59), dataout);

    and2(60) <= write and decoder(60) after 14 ns;
    d60: dlatch port map (datain, and2(60), latchout);
    t60: tris8  port map (latchout, decoder(60), dataout);

    and2(61) <= write and decoder(61) after 14 ns;
    d61: dlatch port map (datain, and2(61), latchout);
    t61: tris8  port map (latchout, decoder(61), dataout);

    and2(62) <= write and decoder(62) after 14 ns;
    d62: dlatch port map (datain, and2(62), latchout);
    t62: tris8  port map (latchout, decoder(62), dataout);

    and2(63) <= write and decoder(63) after 14 ns;
    d63: dlatch port map (datain, and2(63), latchout);
    t63: tris8  port map (latchout, decoder(63), dataout);

    and2(64) <= write and decoder(64) after 14 ns;
    d64: dlatch port map (datain, and2(64), latchout);
    t64: tris8  port map (latchout, decoder(64), dataout);

    and2(65) <= write and decoder(65) after 14 ns;
    d65: dlatch port map (datain, and2(65), latchout);
    t65: tris8  port map (latchout, decoder(65), dataout);

    and2(66) <= write and decoder(66) after 14 ns;
    d66: dlatch port map (datain, and2(66), latchout);
    t66: tris8  port map (latchout, decoder(66), dataout);

    and2(67) <= write and decoder(67) after 14 ns;
    d67: dlatch port map (datain, and2(67), latchout);
    t67: tris8  port map (latchout, decoder(67), dataout);

    and2(68) <= write and decoder(68) after 14 ns;
    d68: dlatch port map (datain, and2(68), latchout);
    t68: tris8  port map (latchout, decoder(68), dataout);

    and2(69) <= write and decoder(69) after 14 ns;
    d69: dlatch port map (datain, and2(69), latchout);
    t69: tris8  port map (latchout, decoder(69), dataout);

    and2(70) <= write and decoder(70) after 14 ns;
    d70: dlatch port map (datain, and2(70), latchout);
    t70: tris8  port map (latchout, decoder(70), dataout);

    and2(71) <= write and decoder(71) after 14 ns;
    d71: dlatch port map (datain, and2(71), latchout);
    t71: tris8  port map (latchout, decoder(71), dataout);

    and2(72) <= write and decoder(72) after 14 ns;
    d72: dlatch port map (datain, and2(72), latchout);
    t72: tris8  port map (latchout, decoder(72), dataout);

    and2(73) <= write and decoder(73) after 14 ns;
    d73: dlatch port map (datain, and2(73), latchout);
    t73: tris8  port map (latchout, decoder(73), dataout);

    and2(74) <= write and decoder(74) after 14 ns;
    d74: dlatch port map (datain, and2(74), latchout);
    t74: tris8  port map (latchout, decoder(74), dataout);

    and2(75) <= write and decoder(75) after 14 ns;
    d75: dlatch port map (datain, and2(75), latchout);
    t75: tris8  port map (latchout, decoder(75), dataout);

    and2(76) <= write and decoder(76) after 14 ns;
    d76: dlatch port map (datain, and2(76), latchout);
    t76: tris8  port map (latchout, decoder(76), dataout);

    and2(77) <= write and decoder(77) after 14 ns;
    d77: dlatch port map (datain, and2(77), latchout);
    t77: tris8  port map (latchout, decoder(77), dataout);

    and2(78) <= write and decoder(78) after 14 ns;
    d78: dlatch port map (datain, and2(78), latchout);
    t78: tris8  port map (latchout, decoder(78), dataout);

    and2(79) <= write and decoder(79) after 14 ns;
    d79: dlatch port map (datain, and2(79), latchout);
    t79: tris8  port map (latchout, decoder(79), dataout);

    and2(80) <= write and decoder(80) after 14 ns;
    d80: dlatch port map (datain, and2(80), latchout);
    t80: tris8  port map (latchout, decoder(80), dataout);

    and2(81) <= write and decoder(81) after 14 ns;
    d81: dlatch port map (datain, and2(81), latchout);
    t81: tris8  port map (latchout, decoder(81), dataout);

    and2(82) <= write and decoder(82) after 14 ns;
    d82: dlatch port map (datain, and2(82), latchout);
    t82: tris8  port map (latchout, decoder(82), dataout);

    and2(83) <= write and decoder(83) after 14 ns;
    d83: dlatch port map (datain, and2(83), latchout);
    t83: tris8  port map (latchout, decoder(83), dataout);

    and2(84) <= write and decoder(84) after 14 ns;
    d84: dlatch port map (datain, and2(84), latchout);
    t84: tris8  port map (latchout, decoder(84), dataout);

    and2(85) <= write and decoder(85) after 14 ns;
    d85: dlatch port map (datain, and2(85), latchout);
    t85: tris8  port map (latchout, decoder(85), dataout);

    and2(86) <= write and decoder(86) after 14 ns;
    d86: dlatch port map (datain, and2(86), latchout);
    t86: tris8  port map (latchout, decoder(86), dataout);

    and2(87) <= write and decoder(87) after 14 ns;
    d87: dlatch port map (datain, and2(87), latchout);
    t87: tris8  port map (latchout, decoder(87), dataout);

    and2(88) <= write and decoder(88) after 14 ns;
    d88: dlatch port map (datain, and2(88), latchout);
    t88: tris8  port map (latchout, decoder(88), dataout);

    and2(89) <= write and decoder(89) after 14 ns;
    d89: dlatch port map (datain, and2(89), latchout);
    t89: tris8  port map (latchout, decoder(89), dataout);

    and2(90) <= write and decoder(90) after 14 ns;
    d90: dlatch port map (datain, and2(90), latchout);
    t90: tris8  port map (latchout, decoder(90), dataout);

    and2(91) <= write and decoder(91) after 14 ns;
    d91: dlatch port map (datain, and2(91), latchout);
    t91: tris8  port map (latchout, decoder(91), dataout);

    and2(92) <= write and decoder(92) after 14 ns;
    d92: dlatch port map (datain, and2(92), latchout);
    t92: tris8  port map (latchout, decoder(92), dataout);

    and2(93) <= write and decoder(93) after 14 ns;
    d93: dlatch port map (datain, and2(93), latchout);
    t93: tris8  port map (latchout, decoder(93), dataout);

    and2(94) <= write and decoder(94) after 14 ns;
    d94: dlatch port map (datain, and2(94), latchout);
    t94: tris8  port map (latchout, decoder(94), dataout);

    and2(95) <= write and decoder(95) after 14 ns;
    d95: dlatch port map (datain, and2(95), latchout);
    t95: tris8  port map (latchout, decoder(95), dataout);

    and2(96) <= write and decoder(96) after 14 ns;
    d96: dlatch port map (datain, and2(96), latchout);
    t96: tris8  port map (latchout, decoder(96), dataout);

    and2(97) <= write and decoder(97) after 14 ns;
    d97: dlatch port map (datain, and2(97), latchout);
    t97: tris8  port map (latchout, decoder(97), dataout);

    and2(98) <= write and decoder(98) after 14 ns;
    d98: dlatch port map (datain, and2(98), latchout);
    t98: tris8  port map (latchout, decoder(98), dataout);

    and2(99) <= write and decoder(99) after 14 ns;
    d99: dlatch port map (datain, and2(99), latchout);
    t99: tris8  port map (latchout, decoder(99), dataout);

    and2(100) <= write and decoder(100) after 14 ns;
    d100: dlatch port map (datain, and2(100), latchout);
    t100: tris8  port map (latchout, decoder(100), dataout);

    and2(101) <= write and decoder(101) after 14 ns;
    d101: dlatch port map (datain, and2(101), latchout);
    t101: tris8  port map (latchout, decoder(101), dataout);

    and2(102) <= write and decoder(102) after 14 ns;
    d102: dlatch port map (datain, and2(102), latchout);
    t102: tris8  port map (latchout, decoder(102), dataout);

    and2(103) <= write and decoder(103) after 14 ns;
    d103: dlatch port map (datain, and2(103), latchout);
    t103: tris8  port map (latchout, decoder(103), dataout);

    and2(104) <= write and decoder(104) after 14 ns;
    d104: dlatch port map (datain, and2(104), latchout);
    t104: tris8  port map (latchout, decoder(104), dataout);

    and2(105) <= write and decoder(105) after 14 ns;
    d105: dlatch port map (datain, and2(105), latchout);
    t105: tris8  port map (latchout, decoder(105), dataout);

    and2(106) <= write and decoder(106) after 14 ns;
    d106: dlatch port map (datain, and2(106), latchout);
    t106: tris8  port map (latchout, decoder(106), dataout);

    and2(107) <= write and decoder(107) after 14 ns;
    d107: dlatch port map (datain, and2(107), latchout);
    t107: tris8  port map (latchout, decoder(107), dataout);

    and2(108) <= write and decoder(108) after 14 ns;
    d108: dlatch port map (datain, and2(108), latchout);
    t108: tris8  port map (latchout, decoder(108), dataout);

    and2(109) <= write and decoder(109) after 14 ns;
    d109: dlatch port map (datain, and2(109), latchout);
    t109: tris8  port map (latchout, decoder(109), dataout);

    and2(110) <= write and decoder(110) after 14 ns;
    d110: dlatch port map (datain, and2(110), latchout);
    t110: tris8  port map (latchout, decoder(110), dataout);

    and2(111) <= write and decoder(111) after 14 ns;
    d111: dlatch port map (datain, and2(111), latchout);
    t111: tris8  port map (latchout, decoder(111), dataout);

    and2(112) <= write and decoder(112) after 14 ns;
    d112: dlatch port map (datain, and2(112), latchout);
    t112: tris8  port map (latchout, decoder(112), dataout);

    and2(113) <= write and decoder(113) after 14 ns;
    d113: dlatch port map (datain, and2(113), latchout);
    t113: tris8  port map (latchout, decoder(113), dataout);

    and2(114) <= write and decoder(114) after 14 ns;
    d114: dlatch port map (datain, and2(114), latchout);
    t114: tris8  port map (latchout, decoder(114), dataout);

    and2(115) <= write and decoder(115) after 14 ns;
    d115: dlatch port map (datain, and2(115), latchout);
    t115: tris8  port map (latchout, decoder(115), dataout);

    and2(116) <= write and decoder(116) after 14 ns;
    d116: dlatch port map (datain, and2(116), latchout);
    t116: tris8  port map (latchout, decoder(116), dataout);

    and2(117) <= write and decoder(117) after 14 ns;
    d117: dlatch port map (datain, and2(117), latchout);
    t117: tris8  port map (latchout, decoder(117), dataout);

    and2(118) <= write and decoder(118) after 14 ns;
    d118: dlatch port map (datain, and2(118), latchout);
    t118: tris8  port map (latchout, decoder(118), dataout);

    and2(119) <= write and decoder(119) after 14 ns;
    d119: dlatch port map (datain, and2(119), latchout);
    t119: tris8  port map (latchout, decoder(119), dataout);

    and2(120) <= write and decoder(120) after 14 ns;
    d120: dlatch port map (datain, and2(120), latchout);
    t120: tris8  port map (latchout, decoder(120), dataout);

    and2(121) <= write and decoder(121) after 14 ns;
    d121: dlatch port map (datain, and2(121), latchout);
    t121: tris8  port map (latchout, decoder(121), dataout);

    and2(122) <= write and decoder(122) after 14 ns;
    d122: dlatch port map (datain, and2(122), latchout);
    t122: tris8  port map (latchout, decoder(122), dataout);

    and2(123) <= write and decoder(123) after 14 ns;
    d123: dlatch port map (datain, and2(123), latchout);
    t123: tris8  port map (latchout, decoder(123), dataout);

    and2(124) <= write and decoder(124) after 14 ns;
    d124: dlatch port map (datain, and2(124), latchout);
    t124: tris8  port map (latchout, decoder(124), dataout);

    and2(125) <= write and decoder(125) after 14 ns;
    d125: dlatch port map (datain, and2(125), latchout);
    t125: tris8  port map (latchout, decoder(125), dataout);

    and2(126) <= write and decoder(126) after 14 ns;
    d126: dlatch port map (datain, and2(126), latchout);
    t126: tris8  port map (latchout, decoder(126), dataout);

    and2(127) <= write and decoder(127) after 14 ns;
    d127: dlatch port map (datain, and2(127), latchout);
    t127: tris8  port map (latchout, decoder(127), dataout);

    and2(128) <= write and decoder(128) after 14 ns;
    d128: dlatch port map (datain, and2(128), latchout);
    t128: tris8  port map (latchout, decoder(128), dataout);

    and2(129) <= write and decoder(129) after 14 ns;
    d129: dlatch port map (datain, and2(129), latchout);
    t129: tris8  port map (latchout, decoder(129), dataout);

    and2(130) <= write and decoder(130) after 14 ns;
    d130: dlatch port map (datain, and2(130), latchout);
    t130: tris8  port map (latchout, decoder(130), dataout);

    and2(131) <= write and decoder(131) after 14 ns;
    d131: dlatch port map (datain, and2(131), latchout);
    t131: tris8  port map (latchout, decoder(131), dataout);

    and2(132) <= write and decoder(132) after 14 ns;
    d132: dlatch port map (datain, and2(132), latchout);
    t132: tris8  port map (latchout, decoder(132), dataout);

    and2(133) <= write and decoder(133) after 14 ns;
    d133: dlatch port map (datain, and2(133), latchout);
    t133: tris8  port map (latchout, decoder(133), dataout);

    and2(134) <= write and decoder(134) after 14 ns;
    d134: dlatch port map (datain, and2(134), latchout);
    t134: tris8  port map (latchout, decoder(134), dataout);

    and2(135) <= write and decoder(135) after 14 ns;
    d135: dlatch port map (datain, and2(135), latchout);
    t135: tris8  port map (latchout, decoder(135), dataout);

    and2(136) <= write and decoder(136) after 14 ns;
    d136: dlatch port map (datain, and2(136), latchout);
    t136: tris8  port map (latchout, decoder(136), dataout);

    and2(137) <= write and decoder(137) after 14 ns;
    d137: dlatch port map (datain, and2(137), latchout);
    t137: tris8  port map (latchout, decoder(137), dataout);

    and2(138) <= write and decoder(138) after 14 ns;
    d138: dlatch port map (datain, and2(138), latchout);
    t138: tris8  port map (latchout, decoder(138), dataout);

    and2(139) <= write and decoder(139) after 14 ns;
    d139: dlatch port map (datain, and2(139), latchout);
    t139: tris8  port map (latchout, decoder(139), dataout);

    and2(140) <= write and decoder(140) after 14 ns;
    d140: dlatch port map (datain, and2(140), latchout);
    t140: tris8  port map (latchout, decoder(140), dataout);

    and2(141) <= write and decoder(141) after 14 ns;
    d141: dlatch port map (datain, and2(141), latchout);
    t141: tris8  port map (latchout, decoder(141), dataout);

    and2(142) <= write and decoder(142) after 14 ns;
    d142: dlatch port map (datain, and2(142), latchout);
    t142: tris8  port map (latchout, decoder(142), dataout);

    and2(143) <= write and decoder(143) after 14 ns;
    d143: dlatch port map (datain, and2(143), latchout);
    t143: tris8  port map (latchout, decoder(143), dataout);

    and2(144) <= write and decoder(144) after 14 ns;
    d144: dlatch port map (datain, and2(144), latchout);
    t144: tris8  port map (latchout, decoder(144), dataout);

    and2(145) <= write and decoder(145) after 14 ns;
    d145: dlatch port map (datain, and2(145), latchout);
    t145: tris8  port map (latchout, decoder(145), dataout);

    and2(146) <= write and decoder(146) after 14 ns;
    d146: dlatch port map (datain, and2(146), latchout);
    t146: tris8  port map (latchout, decoder(146), dataout);

    and2(147) <= write and decoder(147) after 14 ns;
    d147: dlatch port map (datain, and2(147), latchout);
    t147: tris8  port map (latchout, decoder(147), dataout);

    and2(148) <= write and decoder(148) after 14 ns;
    d148: dlatch port map (datain, and2(148), latchout);
    t148: tris8  port map (latchout, decoder(148), dataout);

    and2(149) <= write and decoder(149) after 14 ns;
    d149: dlatch port map (datain, and2(149), latchout);
    t149: tris8  port map (latchout, decoder(149), dataout);

    and2(150) <= write and decoder(150) after 14 ns;
    d150: dlatch port map (datain, and2(150), latchout);
    t150: tris8  port map (latchout, decoder(150), dataout);

    and2(151) <= write and decoder(151) after 14 ns;
    d151: dlatch port map (datain, and2(151), latchout);
    t151: tris8  port map (latchout, decoder(151), dataout);

    and2(152) <= write and decoder(152) after 14 ns;
    d152: dlatch port map (datain, and2(152), latchout);
    t152: tris8  port map (latchout, decoder(152), dataout);

    and2(153) <= write and decoder(153) after 14 ns;
    d153: dlatch port map (datain, and2(153), latchout);
    t153: tris8  port map (latchout, decoder(153), dataout);

    and2(154) <= write and decoder(154) after 14 ns;
    d154: dlatch port map (datain, and2(154), latchout);
    t154: tris8  port map (latchout, decoder(154), dataout);

    and2(155) <= write and decoder(155) after 14 ns;
    d155: dlatch port map (datain, and2(155), latchout);
    t155: tris8  port map (latchout, decoder(155), dataout);

    and2(156) <= write and decoder(156) after 14 ns;
    d156: dlatch port map (datain, and2(156), latchout);
    t156: tris8  port map (latchout, decoder(156), dataout);

    and2(157) <= write and decoder(157) after 14 ns;
    d157: dlatch port map (datain, and2(157), latchout);
    t157: tris8  port map (latchout, decoder(157), dataout);

    and2(158) <= write and decoder(158) after 14 ns;
    d158: dlatch port map (datain, and2(158), latchout);
    t158: tris8  port map (latchout, decoder(158), dataout);

    and2(159) <= write and decoder(159) after 14 ns;
    d159: dlatch port map (datain, and2(159), latchout);
    t159: tris8  port map (latchout, decoder(159), dataout);

    and2(160) <= write and decoder(160) after 14 ns;
    d160: dlatch port map (datain, and2(160), latchout);
    t160: tris8  port map (latchout, decoder(160), dataout);

    and2(161) <= write and decoder(161) after 14 ns;
    d161: dlatch port map (datain, and2(161), latchout);
    t161: tris8  port map (latchout, decoder(161), dataout);

    and2(162) <= write and decoder(162) after 14 ns;
    d162: dlatch port map (datain, and2(162), latchout);
    t162: tris8  port map (latchout, decoder(162), dataout);

    and2(163) <= write and decoder(163) after 14 ns;
    d163: dlatch port map (datain, and2(163), latchout);
    t163: tris8  port map (latchout, decoder(163), dataout);

    and2(164) <= write and decoder(164) after 14 ns;
    d164: dlatch port map (datain, and2(164), latchout);
    t164: tris8  port map (latchout, decoder(164), dataout);

    and2(165) <= write and decoder(165) after 14 ns;
    d165: dlatch port map (datain, and2(165), latchout);
    t165: tris8  port map (latchout, decoder(165), dataout);

    and2(166) <= write and decoder(166) after 14 ns;
    d166: dlatch port map (datain, and2(166), latchout);
    t166: tris8  port map (latchout, decoder(166), dataout);

    and2(167) <= write and decoder(167) after 14 ns;
    d167: dlatch port map (datain, and2(167), latchout);
    t167: tris8  port map (latchout, decoder(167), dataout);

    and2(168) <= write and decoder(168) after 14 ns;
    d168: dlatch port map (datain, and2(168), latchout);
    t168: tris8  port map (latchout, decoder(168), dataout);

    and2(169) <= write and decoder(169) after 14 ns;
    d169: dlatch port map (datain, and2(169), latchout);
    t169: tris8  port map (latchout, decoder(169), dataout);

    and2(170) <= write and decoder(170) after 14 ns;
    d170: dlatch port map (datain, and2(170), latchout);
    t170: tris8  port map (latchout, decoder(170), dataout);

    and2(171) <= write and decoder(171) after 14 ns;
    d171: dlatch port map (datain, and2(171), latchout);
    t171: tris8  port map (latchout, decoder(171), dataout);

    and2(172) <= write and decoder(172) after 14 ns;
    d172: dlatch port map (datain, and2(172), latchout);
    t172: tris8  port map (latchout, decoder(172), dataout);

    and2(173) <= write and decoder(173) after 14 ns;
    d173: dlatch port map (datain, and2(173), latchout);
    t173: tris8  port map (latchout, decoder(173), dataout);

    and2(174) <= write and decoder(174) after 14 ns;
    d174: dlatch port map (datain, and2(174), latchout);
    t174: tris8  port map (latchout, decoder(174), dataout);

    and2(175) <= write and decoder(175) after 14 ns;
    d175: dlatch port map (datain, and2(175), latchout);
    t175: tris8  port map (latchout, decoder(175), dataout);

    and2(176) <= write and decoder(176) after 14 ns;
    d176: dlatch port map (datain, and2(176), latchout);
    t176: tris8  port map (latchout, decoder(176), dataout);

    and2(177) <= write and decoder(177) after 14 ns;
    d177: dlatch port map (datain, and2(177), latchout);
    t177: tris8  port map (latchout, decoder(177), dataout);

    and2(178) <= write and decoder(178) after 14 ns;
    d178: dlatch port map (datain, and2(178), latchout);
    t178: tris8  port map (latchout, decoder(178), dataout);

    and2(179) <= write and decoder(179) after 14 ns;
    d179: dlatch port map (datain, and2(179), latchout);
    t179: tris8  port map (latchout, decoder(179), dataout);

    and2(180) <= write and decoder(180) after 14 ns;
    d180: dlatch port map (datain, and2(180), latchout);
    t180: tris8  port map (latchout, decoder(180), dataout);

    and2(181) <= write and decoder(181) after 14 ns;
    d181: dlatch port map (datain, and2(181), latchout);
    t181: tris8  port map (latchout, decoder(181), dataout);

    and2(182) <= write and decoder(182) after 14 ns;
    d182: dlatch port map (datain, and2(182), latchout);
    t182: tris8  port map (latchout, decoder(182), dataout);

    and2(183) <= write and decoder(183) after 14 ns;
    d183: dlatch port map (datain, and2(183), latchout);
    t183: tris8  port map (latchout, decoder(183), dataout);

    and2(184) <= write and decoder(184) after 14 ns;
    d184: dlatch port map (datain, and2(184), latchout);
    t184: tris8  port map (latchout, decoder(184), dataout);

    and2(185) <= write and decoder(185) after 14 ns;
    d185: dlatch port map (datain, and2(185), latchout);
    t185: tris8  port map (latchout, decoder(185), dataout);

    and2(186) <= write and decoder(186) after 14 ns;
    d186: dlatch port map (datain, and2(186), latchout);
    t186: tris8  port map (latchout, decoder(186), dataout);

    and2(187) <= write and decoder(187) after 14 ns;
    d187: dlatch port map (datain, and2(187), latchout);
    t187: tris8  port map (latchout, decoder(187), dataout);

    and2(188) <= write and decoder(188) after 14 ns;
    d188: dlatch port map (datain, and2(188), latchout);
    t188: tris8  port map (latchout, decoder(188), dataout);

    and2(189) <= write and decoder(189) after 14 ns;
    d189: dlatch port map (datain, and2(189), latchout);
    t189: tris8  port map (latchout, decoder(189), dataout);

    and2(190) <= write and decoder(190) after 14 ns;
    d190: dlatch port map (datain, and2(190), latchout);
    t190: tris8  port map (latchout, decoder(190), dataout);

    and2(191) <= write and decoder(191) after 14 ns;
    d191: dlatch port map (datain, and2(191), latchout);
    t191: tris8  port map (latchout, decoder(191), dataout);

    and2(192) <= write and decoder(192) after 14 ns;
    d192: dlatch port map (datain, and2(192), latchout);
    t192: tris8  port map (latchout, decoder(192), dataout);

    and2(193) <= write and decoder(193) after 14 ns;
    d193: dlatch port map (datain, and2(193), latchout);
    t193: tris8  port map (latchout, decoder(193), dataout);

    and2(194) <= write and decoder(194) after 14 ns;
    d194: dlatch port map (datain, and2(194), latchout);
    t194: tris8  port map (latchout, decoder(194), dataout);

    and2(195) <= write and decoder(195) after 14 ns;
    d195: dlatch port map (datain, and2(195), latchout);
    t195: tris8  port map (latchout, decoder(195), dataout);

    and2(196) <= write and decoder(196) after 14 ns;
    d196: dlatch port map (datain, and2(196), latchout);
    t196: tris8  port map (latchout, decoder(196), dataout);

    and2(197) <= write and decoder(197) after 14 ns;
    d197: dlatch port map (datain, and2(197), latchout);
    t197: tris8  port map (latchout, decoder(197), dataout);

    and2(198) <= write and decoder(198) after 14 ns;
    d198: dlatch port map (datain, and2(198), latchout);
    t198: tris8  port map (latchout, decoder(198), dataout);

    and2(199) <= write and decoder(199) after 14 ns;
    d199: dlatch port map (datain, and2(199), latchout);
    t199: tris8  port map (latchout, decoder(199), dataout);

    and2(200) <= write and decoder(200) after 14 ns;
    d200: dlatch port map (datain, and2(200), latchout);
    t200: tris8  port map (latchout, decoder(200), dataout);

    and2(201) <= write and decoder(201) after 14 ns;
    d201: dlatch port map (datain, and2(201), latchout);
    t201: tris8  port map (latchout, decoder(201), dataout);

    and2(202) <= write and decoder(202) after 14 ns;
    d202: dlatch port map (datain, and2(202), latchout);
    t202: tris8  port map (latchout, decoder(202), dataout);

    and2(203) <= write and decoder(203) after 14 ns;
    d203: dlatch port map (datain, and2(203), latchout);
    t203: tris8  port map (latchout, decoder(203), dataout);

    and2(204) <= write and decoder(204) after 14 ns;
    d204: dlatch port map (datain, and2(204), latchout);
    t204: tris8  port map (latchout, decoder(204), dataout);

    and2(205) <= write and decoder(205) after 14 ns;
    d205: dlatch port map (datain, and2(205), latchout);
    t205: tris8  port map (latchout, decoder(205), dataout);

    and2(206) <= write and decoder(206) after 14 ns;
    d206: dlatch port map (datain, and2(206), latchout);
    t206: tris8  port map (latchout, decoder(206), dataout);

    and2(207) <= write and decoder(207) after 14 ns;
    d207: dlatch port map (datain, and2(207), latchout);
    t207: tris8  port map (latchout, decoder(207), dataout);

    and2(208) <= write and decoder(208) after 14 ns;
    d208: dlatch port map (datain, and2(208), latchout);
    t208: tris8  port map (latchout, decoder(208), dataout);

    and2(209) <= write and decoder(209) after 14 ns;
    d209: dlatch port map (datain, and2(209), latchout);
    t209: tris8  port map (latchout, decoder(209), dataout);

    and2(210) <= write and decoder(210) after 14 ns;
    d210: dlatch port map (datain, and2(210), latchout);
    t210: tris8  port map (latchout, decoder(210), dataout);

    and2(211) <= write and decoder(211) after 14 ns;
    d211: dlatch port map (datain, and2(211), latchout);
    t211: tris8  port map (latchout, decoder(211), dataout);

    and2(212) <= write and decoder(212) after 14 ns;
    d212: dlatch port map (datain, and2(212), latchout);
    t212: tris8  port map (latchout, decoder(212), dataout);

    and2(213) <= write and decoder(213) after 14 ns;
    d213: dlatch port map (datain, and2(213), latchout);
    t213: tris8  port map (latchout, decoder(213), dataout);

    and2(214) <= write and decoder(214) after 14 ns;
    d214: dlatch port map (datain, and2(214), latchout);
    t214: tris8  port map (latchout, decoder(214), dataout);

    and2(215) <= write and decoder(215) after 14 ns;
    d215: dlatch port map (datain, and2(215), latchout);
    t215: tris8  port map (latchout, decoder(215), dataout);

    and2(216) <= write and decoder(216) after 14 ns;
    d216: dlatch port map (datain, and2(216), latchout);
    t216: tris8  port map (latchout, decoder(216), dataout);

    and2(217) <= write and decoder(217) after 14 ns;
    d217: dlatch port map (datain, and2(217), latchout);
    t217: tris8  port map (latchout, decoder(217), dataout);

    and2(218) <= write and decoder(218) after 14 ns;
    d218: dlatch port map (datain, and2(218), latchout);
    t218: tris8  port map (latchout, decoder(218), dataout);

    and2(219) <= write and decoder(219) after 14 ns;
    d219: dlatch port map (datain, and2(219), latchout);
    t219: tris8  port map (latchout, decoder(219), dataout);

    and2(220) <= write and decoder(220) after 14 ns;
    d220: dlatch port map (datain, and2(220), latchout);
    t220: tris8  port map (latchout, decoder(220), dataout);

    and2(221) <= write and decoder(221) after 14 ns;
    d221: dlatch port map (datain, and2(221), latchout);
    t221: tris8  port map (latchout, decoder(221), dataout);

    and2(222) <= write and decoder(222) after 14 ns;
    d222: dlatch port map (datain, and2(222), latchout);
    t222: tris8  port map (latchout, decoder(222), dataout);

    and2(223) <= write and decoder(223) after 14 ns;
    d223: dlatch port map (datain, and2(223), latchout);
    t223: tris8  port map (latchout, decoder(223), dataout);

    and2(224) <= write and decoder(224) after 14 ns;
    d224: dlatch port map (datain, and2(224), latchout);
    t224: tris8  port map (latchout, decoder(224), dataout);

    and2(225) <= write and decoder(225) after 14 ns;
    d225: dlatch port map (datain, and2(225), latchout);
    t225: tris8  port map (latchout, decoder(225), dataout);

    and2(226) <= write and decoder(226) after 14 ns;
    d226: dlatch port map (datain, and2(226), latchout);
    t226: tris8  port map (latchout, decoder(226), dataout);

    and2(227) <= write and decoder(227) after 14 ns;
    d227: dlatch port map (datain, and2(227), latchout);
    t227: tris8  port map (latchout, decoder(227), dataout);

    and2(228) <= write and decoder(228) after 14 ns;
    d228: dlatch port map (datain, and2(228), latchout);
    t228: tris8  port map (latchout, decoder(228), dataout);

    and2(229) <= write and decoder(229) after 14 ns;
    d229: dlatch port map (datain, and2(229), latchout);
    t229: tris8  port map (latchout, decoder(229), dataout);

    and2(230) <= write and decoder(230) after 14 ns;
    d230: dlatch port map (datain, and2(230), latchout);
    t230: tris8  port map (latchout, decoder(230), dataout);

    and2(231) <= write and decoder(231) after 14 ns;
    d231: dlatch port map (datain, and2(231), latchout);
    t231: tris8  port map (latchout, decoder(231), dataout);

    and2(232) <= write and decoder(232) after 14 ns;
    d232: dlatch port map (datain, and2(232), latchout);
    t232: tris8  port map (latchout, decoder(232), dataout);

    and2(233) <= write and decoder(233) after 14 ns;
    d233: dlatch port map (datain, and2(233), latchout);
    t233: tris8  port map (latchout, decoder(233), dataout);

    and2(234) <= write and decoder(234) after 14 ns;
    d234: dlatch port map (datain, and2(234), latchout);
    t234: tris8  port map (latchout, decoder(234), dataout);

    and2(235) <= write and decoder(235) after 14 ns;
    d235: dlatch port map (datain, and2(235), latchout);
    t235: tris8  port map (latchout, decoder(235), dataout);

    and2(236) <= write and decoder(236) after 14 ns;
    d236: dlatch port map (datain, and2(236), latchout);
    t236: tris8  port map (latchout, decoder(236), dataout);

    and2(237) <= write and decoder(237) after 14 ns;
    d237: dlatch port map (datain, and2(237), latchout);
    t237: tris8  port map (latchout, decoder(237), dataout);

    and2(238) <= write and decoder(238) after 14 ns;
    d238: dlatch port map (datain, and2(238), latchout);
    t238: tris8  port map (latchout, decoder(238), dataout);

    and2(239) <= write and decoder(239) after 14 ns;
    d239: dlatch port map (datain, and2(239), latchout);
    t239: tris8  port map (latchout, decoder(239), dataout);

    and2(240) <= write and decoder(240) after 14 ns;
    d240: dlatch port map (datain, and2(240), latchout);
    t240: tris8  port map (latchout, decoder(240), dataout);

    and2(241) <= write and decoder(241) after 14 ns;
    d241: dlatch port map (datain, and2(241), latchout);
    t241: tris8  port map (latchout, decoder(241), dataout);

    and2(242) <= write and decoder(242) after 14 ns;
    d242: dlatch port map (datain, and2(242), latchout);
    t242: tris8  port map (latchout, decoder(242), dataout);

    and2(243) <= write and decoder(243) after 14 ns;
    d243: dlatch port map (datain, and2(243), latchout);
    t243: tris8  port map (latchout, decoder(243), dataout);

    and2(244) <= write and decoder(244) after 14 ns;
    d244: dlatch port map (datain, and2(244), latchout);
    t244: tris8  port map (latchout, decoder(244), dataout);

    and2(245) <= write and decoder(245) after 14 ns;
    d245: dlatch port map (datain, and2(245), latchout);
    t245: tris8  port map (latchout, decoder(245), dataout);

    and2(246) <= write and decoder(246) after 14 ns;
    d246: dlatch port map (datain, and2(246), latchout);
    t246: tris8  port map (latchout, decoder(246), dataout);

    and2(247) <= write and decoder(247) after 14 ns;
    d247: dlatch port map (datain, and2(247), latchout);
    t247: tris8  port map (latchout, decoder(247), dataout);

    and2(248) <= write and decoder(248) after 14 ns;
    d248: dlatch port map (datain, and2(248), latchout);
    t248: tris8  port map (latchout, decoder(248), dataout);

    and2(249) <= write and decoder(249) after 14 ns;
    d249: dlatch port map (datain, and2(249), latchout);
    t249: tris8  port map (latchout, decoder(249), dataout);

    and2(250) <= write and decoder(250) after 14 ns;
    d250: dlatch port map (datain, and2(250), latchout);
    t250: tris8  port map (latchout, decoder(250), dataout);

    and2(251) <= write and decoder(251) after 14 ns;
    d251: dlatch port map (datain, and2(251), latchout);
    t251: tris8  port map (latchout, decoder(251), dataout);

    and2(252) <= write and decoder(252) after 14 ns;
    d252: dlatch port map (datain, and2(252), latchout);
    t252: tris8  port map (latchout, decoder(252), dataout);

    and2(253) <= write and decoder(253) after 14 ns;
    d253: dlatch port map (datain, and2(253), latchout);
    t253: tris8  port map (latchout, decoder(253), dataout);

    and2(254) <= write and decoder(254) after 14 ns;
    d254: dlatch port map (datain, and2(254), latchout);
    t254: tris8  port map (latchout, decoder(254), dataout);

    and2(255) <= write and decoder(255) after 14 ns;
    d255: dlatch port map (datain, and2(255), latchout);
    t255: tris8  port map (latchout, decoder(255), dataout);
end struc;