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-- CSE 471 Project #4 ; 2kbit Static RAM Design
-- Section : 2
-- Designer : Meghan Hoke
-- Date : 10/25/01
-- File : control.vhd
-- Description : read/write control signals
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library IEEE;
use IEEE.std_logic_1164.all;

entity control is
    port(csb, web, oeb : in std_logic;
	 write, read : out std_logic);
end control;

architecture struc of control is

    signal csbnot, webnot, oebnot : std_logic;
    
begin
    csbnot <= not csb after 10 ns;
    webnot <= not web after 10 ns;
    oebnot <= not oeb after 10 ns;

    write <= csbnot and webnot after 14 ns;
    read <= csbnot and oebnot and web after 15 ns;
end struc;