-------------------------------------------------------------------------------
-- CSE 471 Project #5 ; 8-bit Microcontroller Design
-- Section : 2
-- Designer : Meghan Hoke
-- Date : 11/15/01
-- File : dlatch.vhd
-- Description : 1-bit D-Latch
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity dlatch1 is
    
    port (d : in std_logic;
	  write : in std_logic;
	  q : out std_logic);

end dlatch1;

architecture struc of dlatch1 is

    component mux1
	port (d0, d1 : in std_logic;
	      s : in std_logic;
	      z : out std_logic);
    end component;

    for all: mux1 use entity work.mux1(struc);

    signal s : std_logic;

begin  -- struc
    m1: mux1 port map (s, d, write, s);
    q <= s;
end struc;