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-- CSE 471 Project #5 ; 8-bit Microcontroller Design
-- Section : 2
-- Designer : Meghan Hoke
-- Date : 11/15/2001
-- File : fa1.vhd
-- Description : 1-bit full adder
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity fa1 is
    
    port (a, b, ci : in std_logic;
	  s, co : out std_logic);

end fa1;

architecture struc of fa1 is

    signal a_n, b_n, ci_n : std_logic;
    signal x0, x1, x2, y0, y1, y2, y3 : std_logic;
    
begin  -- struc
    a_n <= not a after 10 ns;
    b_n <= not b after 10 ns;
    ci_n <= not ci after 10 ns;
    x0 <= a nand b after 11 ns;
    x1 <= a nand ci after 11 ns;
    x2 <= b nand ci after 11 ns;
    co <= not (x0 and x1 and x2) after 12 ns;
    y0 <= not (a and b and ci) after 12 ns;
    y1 <= not (a_n and b_n and ci) after 12 ns;
    y2 <= not (a_n and b and ci_n) after 12 ns;
    y3 <= not (a and b_n and ci_n) after 12 ns;
    s <= not (y0 and y1 and y2 and y3) after 13 ns;
end struc;