-------------------------------------------------------------------------------
-- CSE 471 Project #5 ; 8-bit Microcontroller Design
-- Section : 2
-- Designer : Meghan Hoke
-- Date : 11/15/2001
-- File : flipflop1.vhd
-- Description : 1-bit Negative Edge Triggered Flip Flop
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity flipflop1 is
    
    port (d : in std_logic;
	  w : in std_logic;
	  q : out std_logic);

end flipflop1;

architecture struc of flipflop1 is

    component dlatch1
	port (d : in std_logic;
	      write : in std_logic;
	      q : out std_logic);
    end component;

    for all: dlatch1 use entity work.dlatch1(struc);

    signal wnot, s : std_logic;

begin  -- struc
    wnot <= not w after 10 ns;
    d1: dlatch1 port map (d, w, s);
    d2: dlatch1 port map (s, wnot, q);
end struc;