-------------------------------------------------------------------------------
-- CSE 471 Project #5 ; 8-bit Microcontroller Design
-- Section : 2
-- Designer : Meghan Hoke
-- Date : 11/15/2001
-- File : id.vhd
-- Description : Instruction Decoder
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity id is
    
    port (reset, clock, t, amod, ld, st : in std_logic;
	  wir, rir, rpc, cpc, sdm, wdr, edt, asb, rw : out std_logic);

end id;

architecture struc of id is

    signal tnot : std_logic;

begin
    tnot <= not t after 10 ns;
    wir <= clock and tnot after 14 ns;
    rir <= reset;
    rpc <= reset;
    cpc <= clock;
    sdm <= amod;
    wdr <= clock and t and ld after 15 ns;
    edt <= clock and t and st after 30 ns;
    asb <= not (clock and t and amod) after 12 ns;
    rw <= not (clock and t and st) after 12 ns;

end struc;