-------------------------------------------------------------------------------
-- CSE 471 Project #5 ; 8-bit Microcontroller Design
-- Section : 2
-- Designer : Meghan Hoke
-- Date : 11/15/2001
-- File : ir.vhd
-- Description : Instruction Register
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity ir is
    
    port (ir : in std_logic_vector(7 downto 0);
	  wir, rir : in std_logic;
	  y : out std_logic_vector(7 downto 0));

end ir;

architecture struc of ir is

    component mux
	port (d0, d1 : in std_logic_vector(7 downto 0);
	      s : in std_logic;
	      z : out std_logic_vector(7 downto 0));
    end component;

    component flipflop
	port (d : in std_logic_vector(7 downto 0);
	      w : in std_logic;
	      q : out std_logic_vector(7 downto 0));
    end component;

    for all: mux use entity work.mux(struc);
    for all: flipflop use entity work.flipflop(struc);

    signal mout : std_logic_vector(7 downto 0);
    signal zero : std_logic_vector(7 downto 0) := "00000000";

begin  -- struc
    m1: mux port map (ir, zero, rir, mout );
    f1: flipflop port map (mout, wir, y);
end struc;