-------------------------------------------------------------------------------
-- CSE 471 Project #5 ; 8-bit Microcontroller Design
-- Section : 2
-- Designer : Meghan Hoke
-- Date : 11/15/2001
-- File : mctrl.vhd
-- Description : 8 bit Microcontroller
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

    entity mctrl is 
        port (reset, ck: in std_logic);  -- reset, clock bit 
    end mctrl;

architecture struc of mctrl is

    component rom
	port( a0, a1, a2, a3, a4, a5, a6, a7 : in std_logic;
	      i0, i1, i2, i3, i4, i5, i6, i7 : out std_logic);
    end component;

    component sram
	port (address : in std_logic_vector(7 downto 0);  -- address bits
	  csb : in std_logic;  		-- chip select bit
	  web : in std_logic;  		-- write enable bit
	  oeb : in std_logic;  		-- output enable bit
	  data : inout std_logic_vector(7 downto 0)); -- datapath bits
    end component;

    component counter
	port (b : in std_logic_vector(7 downto 0);
	      r, w : in std_logic;
              a : out std_logic_vector(7 downto 0));
    end component;

    component mux
        port (d0, d1 : in std_logic_vector(7 downto 0);
	      s : in std_logic;
	      z : out std_logic_vector(7 downto 0));
    end component;

    component flipflop
	port (d : in std_logic_vector(7 downto 0);
	      w : in std_logic;
	      q : out std_logic_vector(7 downto 0));
    end component;

    component tris8
        port (a : in std_logic_vector(7 downto 0);
	      s : in std_logic;  
              z : inout std_logic_vector(7 downto 0));
    end component;

    component sm
	port (reset, clock : in std_logic;
	      t : out std_logic);
    end component;

    component ir
        port (ir : in std_logic_vector(7 downto 0);
	      wir, rir : in std_logic;
	      y : out std_logic_vector(7 downto 0)); 
    end component;

    component id
        port (reset, clock, t, amod, ld, st : in std_logic;
	      wir, rir, rpc, cpc, sdm, wdr, edt, asb, rw : out std_logic); 
    end component;

    for all: rom use entity work.rom(struc);
    for all: sram use entity work.sram(struc);
    for all: counter use entity work.counter(struc);
    for all: mux use entity work.mux(struc);
    for all: flipflop use entity work.flipflop(struc);
    for all: tris8 use entity work.tris8(beha);
    for all: sm use entity work.sm(struc);
    for all: ir use entity work.ir(struc);
    for all: id use entity work.id(struc);

    signal RPC, CPC, SDM, WDR, EDT, RIR, WIR, T : std_logic;
    signal asb, asb_not, rw, oeb : std_logic;
    signal iadr, idat, mdat, ir_out, mux_out, dr_out : std_logic_vector(7 downto 0);
    signal count : std_logic_vector(7 downto 0) := "00000001";  --PC increment
    signal i: integer;  		--for simulation

begin
    pc1: counter port map (count,RPC,CPC,iadr);
    rom1: rom port map (iadr(0),iadr(1),iadr(2),iadr(3),iadr(4),iadr(5),iadr(6),iadr(7),idat(0),idat(1),idat(2),idat(3),idat(4),idat(5),idat(6),idat(7));
    sm1: sm port map (reset, ck, T);
    ir1: ir port map (idat,WIR,RIR,ir_out);
    id1: id port map (reset,ck,T,ir_out(5),ir_out(6),ir_out(7),WIR,RIR,RPC,CPC,SDM,WDR,EDT,asb,rw);
    asb_not <= not asb after 10 ns;
    oeb <= asb_not nand rw after 11 ns;
    ram1: sram port map (idat,asb,rw,oeb,mdat);
    mux1: mux port map (idat,mdat,SDM,mux_out);
    dr1: flipflop port map (mux_out,WDR,dr_out);
    ts1: tris8 port map (dr_out,EDT,mdat); 
end struc;