-------------------------------------------------------------------------------
-- CSE 471 Project #5 ; 8-bit Microcontroller Design
-- Section : 2
-- Designer : Meghan Hoke
-- Date : 11/15/2001
-- File : mux.vhd
-- Description : 2 to 1 8-bit multiplexer
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity mux is
    
    port (d0, d1 : in std_logic_vector(7 downto 0);
	  s : in std_logic;
	  z : out std_logic_vector(7 downto 0));

end mux;

architecture struc of mux is

    signal sinv, s1, s2, s3, s4, s5, s6, s7, s8 : std_logic;
    signal s9, s10, s11, s12, s13, s14, s15, s16: std_logic;

begin
    sinv <= not s after 10 ns;

    s1 <= d1(0) nand s after 11 ns;
    s2 <= d0(0) nand sinv after 11 ns;
    z(0) <= s1 nand s2 after 11 ns;

    s3 <= d1(1) nand s after 11 ns;
    s4 <= d0(1) nand sinv after 11 ns;
    z(1) <= s3 nand s4 after 11 ns;

    s5 <= d1(2) nand s after 11 ns;
    s6 <= d0(2) nand sinv after 11 ns;
    z(2) <= s5 nand s6 after 11 ns;

    s7 <= d1(3) nand s after 11 ns;
    s8 <= d0(3) nand sinv after 11 ns;
    z(3) <= s7 nand s8 after 11 ns;

    s9 <= d1(4) nand s after 11 ns;
    s10 <= d0(4) nand sinv after 11 ns;
    z(4) <= s9 nand s10 after 11 ns;

    s11 <= d1(5) nand s after 11 ns;
    s12 <= d0(5) nand sinv after 11 ns;
    z(5) <= s11 nand s12 after 11 ns;

    s13 <= d1(6) nand s after 11 ns;
    s14 <= d0(6) nand sinv after 11 ns;
    z(6) <= s13 nand s14 after 11 ns;

    s15 <= d1(7) nand s after 11 ns;
    s16 <= d0(7) nand sinv after 11 ns;
    z(7) <= s15 nand s16 after 11 ns;
end struc;