-------------------------------------------------------------------------------
-- CSE 471 Project #5 ; 8-bit Microcontroller Design
-- Section : 2
-- Designer : Meghan Hoke
-- Date : 11/15/2001
-- File : sm.vhd
-- Description : State Machine
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity sm is
    
    port (reset, clock : in std_logic;
	  t : out std_logic);

end sm;

architecture struc of sm is

    component mux1
	port (d0, d1, s : in std_logic;
	      z : out std_logic);
    end component;
    
    component flipflop1
	port (d, w : in std_logic;
	      q : out std_logic);
    end component;

    for all: mux1 use entity work.mux1(struc);
    for all: flipflop1 use entity work.flipflop1(struc);

    signal tnot, z, q : std_logic;
    signal zero : std_logic := '0';

begin  -- struc
    tnot <= not q after 10 ns;
    m1: mux1 port map (tnot, zero, reset, z);
    f1: flipflop1 port map (z, clock, q);
    t <= q;
end struc;