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-- CSE 471 Project #4 ; VHDL Design
-- Section : 2
-- Designer : Meghan Hoke
-- Date : 10/25/01
-- File : tris.vhd
-- Description : Tri-State Buffer
-----------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity tris is
   port(a, s : in  std_logic;  
        z : inout std_logic);
end tris;

architecture beha of tris is
begin

    z <= a after 11 ns when (s='1') 
                             else 'Z' after 11 ns;

end beha;