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-- CSE 471 Project #4 ; VHDL Design
-- Section : 2
-- Designer : Meghan Hoke
-- Date : 10/25/01
-- File : tris8.vhd
-- Description : 8-bit Tri-State Buffer
-----------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity tris8 is
   port(a : in std_logic_vector(7 downto 0);
	s : in std_logic;  
        z : inout std_logic_vector(7 downto 0));
end tris8;

architecture beha of tris8 is

    component tris
	port (a, s : in std_logic;
	      z : inout std_logic);
    end component;

    for all: tris use entity work.tris(beha);
    
begin
    tri0: tris port map (a(0), s, z(0));
    tri1: tris port map (a(1), s, z(1));
    tri2: tris port map (a(2), s, z(2));
    tri3: tris port map (a(3), s, z(3));
    tri4: tris port map (a(4), s, z(4));
    tri5: tris port map (a(5), s, z(5));
    tri6: tris port map (a(6), s, z(6));
    tri7: tris port map (a(7), s, z(7));
end beha;